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general description the MAX1122 is a monolithic 10-bit, 170msps analog- to-digital converter (adc) optimized for outstanding dynamic performance at high if frequencies up to 500mhz. the product operates with conversion rates of up to 170msps while consuming only 460mw. at 170msps and an input frequency of 100mhz, the MAX1122 achieves a spurious-free dynamic range (sfdr) of 72dbc. its excellent signal-to-noise ratio (snr) of 57.5db at 10mhz remains flat (within 1db) for input tones up to 500mhz. this makes the MAX1122 ideal for wideband applications such as digital predis- tortion in cellular base-station transceiver systems. the MAX1122 requires a single 1.8v supply. the ana- log input is designed for either differential or single- ended operation and can be ac- or dc-coupled. the adc also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock fre- quencies as high as 340mhz. this helps to reduce the phase noise of the input clock source. a differential lvds sampling clock is recommended for best perfor- mance. the converter? digital outputs are lvds com- patible, and the data format can be selected to be either two? complement or offset binary. the MAX1122 is available in a 68-pin qfn with exposed paddle (ep) and is specified over the industri- al (-40? to +85?) temperature range. for pin-compatible, higher speed versions of the MAX1122, refer to the max1123 (210msps) and the max1124 (250msps) data sheets. for a higher speed, pin-compatible 8-bit version of the MAX1122, refer to the max1121 data sheet. applications wireless and wired broadband communication cable-head end systems digital predistortion receivers communications test equipment radar and satellite subsystems antenna array processing features 170msps conversion rate snr = 57.1db/56.5db at f in = 100mhz/500mhz sfdr = 72dbc/63.5dbc at f in = 100mhz/500mhz npr = 53.7db at f notch = 28.8mhz single 1.8v supply 460mw power dissipation at 170msps on-chip track-and-hold and internal reference on-chip selectable divide-by-2 clock input lvds digital outputs with data clock output evaluation kit available (order max1124evkit) MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications ________________________________________________________________ maxim integrated products 1 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 av cc agnd av cc top view av cc ognd ov cc orp orn d9p d9n d8p d8n 52 53 d7p d7n agnd agnd av cc clkn clkp av cc agnd ov cc ognd n.c. ov cc n.c. n.c. n.c. d4p d4n ognd ov cc dclkp dclkn ov cc d3p d3n d2p 35 36 37 d2n d1p d1n agnd inn inp agnd av cc agnd agnd av cc av cc av cc agnd refadj refio agnd 48 d5n av cc 64 agnd 65 66 67 agnd agnd av cc 68 t/b 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 d0n d0p 34 33 49 50 d6n d5p 51 d6p 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 clkdiv 17 MAX1122 ep pin configuration ordering information 19-3027; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX1122egk -40 c to +85 c 68 qfn-ep* * ep = exposed paddle.
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to agnd ......................................................-0.3v to +2.1v ov cc to ognd .....................................................-0.3v to +2.1v av cc to ov cc .......................................................-0.3v to +2.1v agnd to ognd ....................................................-0.3v to +0.3v analog inputs to agnd ...........................-0.3v to (av cc + 0.3v) digital inputs to agnd.............................-0.3v to (av cc + 0.3v) ref, refadj to agnd............................-0.3v to (av cc + 0.3v) digital outputs to ognd .........................-0.3v to (ov cc + 0.3v) esd on all pins (human body model).............................2000v continuous power dissipation (t a = +70 c) 68-pin qfn (derate 41.7mw/ c above +70 c) .........3333mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c maximum current into any pin............................................50ma electrical characteristics (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170mhz, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digital output pins differential r l = 100 ? 1%, c l = 5pf, t a = t min to t max , unless otherwise noted. 25 c guar- anteed by production test, <25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl (note 1) -1.5 0.4 +1.5 lsb differential nonlinearity dnl no missing codes (note 1) -1.0 0.3 +1.5 lsb t a +25 c -25 +25 transfer curve offset v os (note 1) (note 2) -37 +37 lsb offset temperature drift 20 v/ c analog inputs (inp, inn) full-scale input voltage range v fs (note 1) 1100 1250 1375 mv p-p full-scale range temperature drift 130 ppm/ c common-mode input range v cm 1.38 0.18 v input capacitance c in 3pf differential input resistance r in 3.00 4.3 6.25 k ? full-power analog bandwidth fpbw figure 8 600 mhz reference (refio, refadj) reference output voltage v refio 1.18 1.24 1.30 v reference temperature drift 90 ppm/ c refadj input high voltage v refadj used to disable the internal reference (note 2) av cc - 0.3 v sampling characteristics maximum sampling rate f sample (note 2) 170 mhz minimum sampling rate f sample 20 mhz
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 3 electrical characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170mhz, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digital output pins differential r l = 100 ? 1%, c l = 5pf, t a = t min to t max , unless otherwise noted. 25 c guar- anteed by production test, <25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units clock duty cycle set by clock management circuit 40 to 60 % aperture delay t ad 350 ps aperture jitter t aj 0.2 ps rms clock inputs (clkp, clkn) differential clock input amplitude (note 2) 200 500 mv p-p clock input common-mode voltage range 1.15 0.25 v clock differential input resistance r clk 11 25% k ? clock differential input capacitance c clk 5pf dynamic characteristics (at -0.5dbfs) f in = 10mhz, t a +25 c 56.5 57.5 f in = 100mhz, t a +25 c 55.5 57.1 f in = 180mhz 57.1 signal-to-noise ratio snr f in = 500mhz 56.5 db f in = 10mhz, t a +25 c 56 57.4 f in = 100mhz, t a +25 c5557 f in = 180mhz 56.7 signal-to-noise and distortion sinad f in = 500mhz 55.3 db f in = 10mhz, t a +25 c6577 f in = 100mhz, t a +25 c6472 f in = 180mhz 67 spurious-free dynamic range sfdr f in = 500mhz 63.5 dbc f in = 10mhz, t a +25 c -77 f in = 100mhz, t a +25 c -72 f in = 180mhz -67 worst harmonics (hd2 or hd3) f in = 500mhz -63.5 dbc imd 100 f in1 = 99mhz at -7dbfs, f in2 = 101mhz at -7dbfs -79 two-tone intermodulation distortion imd 500 f in1 = 499mhz at -7dbfs, f in2 = 503mhz at -7dbfs -60 dbc lvds digital outputs (d0p/n d9p/n, dclkp/n) differential output voltage |v od | 250 400 mv
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 4 _______________________________________________________________________________________ electrical characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170mhz, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digital output pins differential r l = 100 ? 1%, c l = 5pf, t a = t min to t max , unless otherwise noted. 25 c guar- anteed by production test, <25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units output offset voltage ov os 1.125 1.310 v lvcmos digital inputs (clkdiv, t /b) digital input voltage low v il (note 2) 0.2 x av cc v digital input voltage high v ih (note 2) 0.8 x av cc v timing characteristics clk to data propagation delay t pdl figure 4 1.5 ns clk to dclk propagation delay t cpdl figure 4 3.43 ns data valid to dclk rising edge t cpdl - t adl figure 4 (note 2) 1.67 1.93 2.35 ns lvds output rise-time t rise 20% to 80%, c l = 5pf 460 ps lvds output fall-time t fall 20% to 80%, c l = 5pf 460 ps output data pipeline delay t latency 8 clock cycles power requirements analog supply voltage range av cc (note 2) 1.70 1.8 1.90 v digital supply voltage range ov cc (note 2) 1.70 1.8 1.90 v analog supply i avcc f in = 100mhz (note 2) 210 275 ma digital supply current i ovcc f in = 100mhz (note 2) 45 75 ma analog power dissipation p diss f in = 100mhz (note 2) 460 630 mw offset 1.6 mv/v power-supply rejection ratio (note 3) psrr gain 1.9 %fs/v note 1: static linearity and offset parameters are computed from a best-fit straight line through the code transition points. the full- scale range is defined as 1023 x slope of the line. note 2: parameter guaranteed by design and characterization; t a = t min to t max . note 3: psrr is measured with both analog and digital supplies connected to the same potential.
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 5 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 203040 10 50 60 70 80 90 fft plot (8192-point data record, coherent sampling) MAX1122 toc01 analog input frequency (mhz) amplitude (db) f sample = 170.0057mhz f in = 11.5177mhz a in = -0.5065dbfs snr = 57.7db sfdr = 77.7dbc hd2 = -77.7dbc hd3 = -86.3dbc hd2 hd3 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 203040 10 50 60 70 80 90 fft plot (8192-point data record, coherent sampling) MAX1122 toc02 analog input frequency (mhz) amplitude (db) f sample = 170.0057mhz f in = 60.0374mhz a in = -0.4795dbfs snr = 57.5db sfdr = 77.7dbc hd2 = -79.8dbc hd3 = -77.7dbc hd2 hd3 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 203040 10 50 60 70 80 90 fft plot (8192-point data record, coherent sampling) MAX1122 toc03 analog input frequency (mhz) amplitude (db) f sample = 170.0057mhz f in = 183.5157mhz a in = -0.4706dbfs snr = 56.7db sfdr = 66.8dbc hd2 = -79.3dbc hd3 = -66.8dbc hd2 hd3 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 203040 10 50 60 70 80 90 fft plot (8192-point data record, coherent sampling) MAX1122 toc04 analog input frequency (mhz) amplitude (db) f sample = 170.0057mhz f in = 500.516mhz a in = -0.5155dbfs snr = 55.9db sfdr = 63.5dbc hd2 = -68.6dbc hd3 = -63.5dbc hd3 hd2 snr vs. analog input frequency (f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc05 f in (mhz) snr (db) 400 300 200 100 54 55 57 56 58 59 53 0 500 sfdr vs. analog input frequency (f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc06 f in (mhz) sfdr (dbc) 400 300 200 100 45 50 65 55 60 35 40 70 75 80 30 0 500 hd2/hd3 vs. analog input frequency (f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc07 f in (mhz) hd2/hd3 (dbc) 400 300 200 100 -90 -80 -70 -60 -50 -100 0 500 hd2 hd3 27 37 32 52 47 42 57 62 -28 -16 -12 -24 -20 -8 -4 0 snr vs. analog input amplitude (f sample = 170.0057mhz, f in = 60.0374mhz) MAX1122 toc08 analog input amplitude (dbfs) snr (db) 50 60 55 70 65 75 80 -28 -16 -12 -24 -20 -8 -4 0 sfdr vs. analog input amplitude (f sample = 170.0057mhz, f in = 60.0374mhz) MAX1122 toc09 analog input amplitude (dbfs) sfdr (dbc) typical operating characteristics (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digita l output pins differential r l = 100 ? , t a = +25 c.)
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 6 _______________________________________________________________________________________ -90 -75 -80 -85 -60 -65 -70 -55 -50 -28 -16 -12 -24 -20 -8 -4 0 hd2/hd3 vs. analog input amplitude (f sample = 170.0057mhz, f in = 60.0374mhz) MAX1122 toc10 analog input amplitude (dbfs) hd2/hd3 (dbc) hd2 hd3 snr vs. f sample (f in = 60.0374mhz, a in = -0.5dbfs) MAX1122 toc11 f sample (mhz) snr (db) 140 110 80 50 52 51 54 53 56 55 58 57 60 59 50 20 170 sfdr vs. f sample (f in = 60.0374mhz, a in = -0.5dbfs) MAX1122 toc12 f sample (mhz) sfdr (dbc) 140 110 80 50 50 60 70 80 90 40 20 170 hd2/hd3 vs. f sample (f in = 60.0374mhz, a in = -0.5dbfs) MAX1122 toc13 f sample (mhz) hd2/hd3 (dbc) 140 110 80 50 -92 -84 -76 -68 -60 -100 20 170 hd2 hd3 -100 -80 -90 -60 -70 -40 -50 -30 -10 -20 0 0 203040 10 50 60 70 80 90 two-tone imd plot (8192-point data record, coherent sampling) MAX1122 toc14 analog input frequency (mhz) amplitude (db) f sample = 170.0057mhz f in1 = 99.0109mhz f in2 = 101.0031mhz a in1 = a in2 = -7dbfs imd = -79dbc 2f in2 - f in1 2f in1 - f in2 f in2 f in1 -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0 0.2 0.4 0.3 0.5 256 384 128 0 512 640 768 896 1024 integral nonlinearity vs. digital output code MAX1122 toc15 digital output code inl (lsb) -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0 0.2 0.4 0.3 0.5 256 384 128 512 640 768 896 1024 differential nonlinearity vs. digital output code MAX1122 toc16 digital output code dnl (lsb) 2 0 -2 -4 -6 -8 -10 -12 10 100 1000 gain bandwidth plot (f sample = 170.0057mhz, a in = -0.5dbfs) MAX1122 toc17 analog input frequency (mhz) gain (db) snr vs. temperature (f in = 64.9994mhz, f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc18 temperature ( c) snr (db) 60 35 10 -15 52 51 54 53 56 55 58 57 60 59 50 -40 85 typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digita l output pins differential r l = 100 ? , t a = +25 c.)
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 7 sinad vs. temperature (f in = 64.9994mhz, f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc19 temperature ( c) sinad (db) 60 35 10 -15 60 59 58 57 56 55 54 53 52 51 50 -40 85 sfdr vs. temperature (f in = 64.9994mhz, f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc20 temperature ( c) sfdr (dbc) 60 35 10 -15 55 60 65 70 75 80 50 -40 85 power dissipation vs. f sample (f in = 60.0374mhz, a in = -0.5dbfs) MAX1122 toc21 f sample (mhz) p diss (mw) 140 110 80 50 432 426 444 438 456 450 468 462 480 474 420 20 170 fs voltage vs. fs adjust resistor MAX1122 toc22 fs adjust resistor ( ? ) v fs (v) 900 800 600 700 200 300 400 500 100 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.16 0 1000 resistor value applied between refadj and agnd resistor value applied between refadj and refio figure 6 snr vs. voltage supply (f in = 60.0374mhz, a in = -0.5dbfs) MAX1122 toc23 voltage supply (v) snr (db) 2.0 1.9 1.8 1.7 1.6 60 59 58 57 56 55 54 53 52 51 50 1.5 2.1 av cc = ov cc internal reference vs. supply voltage (f sample = 170.0057mhz) MAX1122 toc24 supply voltage (v) v refio (v) 2.0 1.9 1.8 1.7 1.6 1.2345 1.2350 1.2355 1.2360 1.2365 1.2370 1.2340 1.5 2.1 measured at the refio pin refadj = av cc = ov cc 0.0e+00 4.0e+04 1.2e+05 8.0e+04 1.6e+05 2.0e+05 511 2412 512 513 59838 514 515 53 noise histogram (dc input, 256k-point data record) MAX1122 toc25 digital output noise code counts f sample = 169.984mhz 199841 propagation delay times vs. temperature MAX1122 toc26 temperature ( c) propagation delay (ns) 60 35 10 -15 1 2 3 4 5 6 0 -40 85 t cpdl t pdl typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digita l output pins differential r l = 100 ? , t a = +25 c.)
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 8 _______________________________________________________________________________________ pin description pin name function 1, 6, 11 14, 20, 25, 62, 63, 65 av cc analog supply voltage. bypass each pin with a 0.1f capacitor for best decoupling results. 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67, ep agnd analog converter ground. connect the converter s exposed paddle (ep) to agnd. 3 refio reference input/output. with refadj pulled high through a 1k ? resistor, this i/o port allows an external reference source to be connected to the MAX1122. with refadj pulled low through the same 1k ? resistor, the internal 1.23v bandgap reference is active. 4 refadj reference-adjust input. refadj allows for full-scale range adjustments by placing a resistor or trim potentiometer between refadj and agnd (decreases fs range) or refadj and refio (increases fs range). if refadj is connected to av cc through a 1k ? resistor, the internal reference can be overdriven with an external source connected to refio. if refadj is connected to agnd through a 1k ? resistor, the internal reference is used to determine the full-scale range of the data converter. 8 inp positive analog input terminal 9 inn negative analog input terminal 17 clkdiv clock divider input. this lvcmos-compatible input controls which speed the converter s digital outputs are updated. clkdiv has an internal pulldown resistor: clkdiv = 0: adc updates digital outputs at one-half the input clock rate. clkdiv = 1: adc updates digital outputs at the input clock rate. 22 clkp true clock input. this input requires an lvds-compatible input level to maintain the converter s excellent performance. 23 clkn complementary clock input. this input requires an lvds-compatible input level to maintain the converter s excellent performance. 50 58 57 59 55 54 56 52 51 53 60 30 48 54 36 42 60 66 72 sinad vs. clock duty cycle (f in = 1.4006mhz, f sample = 169.984mhz, a in = -0.5dbfs) MAX1122 toc27 clock duty cycle (%) sinad (db) -100 -80 -90 -60 -70 -50 -40 5 101520253035 noise power ratio plot MAX1122 toc28 analog input frequency (mhz) power spectral density (db) f sample = 170mhz f notch = 28.8mhz npr = 53.7db typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 170.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1f capacitor on refio, internal reference, digita l output pins differential r l = 100 ? , t a = +25 c.)
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 9 pin description (continued) pin name function 26, 45, 61 ognd digital converter ground. ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 ov cc digital supply voltage. bypass with a 0.1f capacitor for best decoupling results. 29 32 n.c. no connection. do not connect to these pins. 33 d0n complementary output bit 0 (lsb) 34 d0p true output bit 0 (lsb) 35 d1n complementary output bit 1 36 d1p true output bit 1 37 d2n complementary output bit 2 38 d2p true output bit 2 39 d3n complementary output bit 3 40 d3p true output bit 3 42 dclkn complementary clock output. this output provides an lvds-compatible output level and can be used to synchronize external devices to the converter clock. there is a 2.1ns delay between clkn and dclkn. 43 dclkp true clock output. this output provides an lvds-compatible output level and can be used to synchronize external devices to the converter clock. there is a 2.1ns delay between clkp and dclkp. 46 d4n complementary output bit 4 47 d4p true output bit 4 48 d5n complementary output bit 5 49 d5p true output bit 5 50 d6n complementary output bit 6 51 d6p true output bit 6 52 d7n complementary output bit 7 53 d7p true output bit 7 54 d8n complementary output bit 8 55 d8p true output bit 8 56 d9n complementary output bit 9 (msb) 57 d9p true output bit 9 (msb) 58 orn complementary output for out-of-range control bit. if an out-of-range condition is detected, bit orn flags this condition by transitioning low. 59 orp true output for out-of-range control bit. if an out-of-range condition is detected, bit orp flags this condition by transitioning high. 68 t /b two s complement or binary output format selection. this lvcmos-compatible input controls the digital output format of the MAX1122. t /b has an internal pulldown resistor. t /b = 0: two s complement output format t /b = 1: binary output format
MAX1122 detailed description?heory of operation the MAX1122 uses a fully differential, pipelined archi- tecture that allows for high-speed conversion, opti- mized accuracy and linearity, while minimizing power consumption and die size. both positive (inp) and negative/complementary analog input terminals (inn) are centered around a common- mode voltage of 1.4v, and accept a differential analog input voltage swing of 0.3125v each, resulting in a typi- cal differential full-scale signal swing of 1.25v p-p . inp and inn are buffered prior to entering each track- and-hold (t/h) stage and are sampled when the differ- ential sampling clock signal transitions high. a 2-bit adc following the first t/h stage then digitizes the sig- nal, and controls a 2-bit digital-to-analog converter (dac). digitized and reference signals are then subtract- ed, resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another t/h amplifier. this process is repeated until the applied input signal has successfully passed through all stages of the 10-bit quantizer. finally, the digital outputs of all stages are combined and corrected for in the digital cor- rection logic to generate the final output code. the result is a 10-bit parallel digital output word in user-selectable two s complement or binary output formats with lvds- compatible output levels. see figure 1 for a more detailed view of the MAX1122 architecture. 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 10 ______________________________________________________________________________________ clock- divider control clock management t/h 10-bit pipeline quantizer core reference lvds data port 10 common-mode buffer input buffer clkdiv clkp clkn inp inn refio refadj 2.2k ? 2.2k ? dclkp dclkn d0p/n?9p/n orp orn MAX1122 figure 1. MAX1122 block diagram av cc agnd inn inp to common-mode input 2.2k ? to common-mode input 2.2k ? figure 2. simplified analog input architecture reference buffer refio refadj av cc av cc / 2 control line to disable reference buffer adc full-scale = reft - refb g 1v 1k ? 0.1 f reference- scaling amplifier reft refb figure 3. simplified reference architecture
analog inputs (inp, inn) inp and inn are the fully differential inputs of the MAX1122. differential inputs usually feature good rejec- tion of even-order harmonics, which allows for enhanced ac performance as the signals are progressing through the analog stages. the MAX1122 analog inputs are self- biased at a common-mode voltage of 1.4v and allow a differential input voltage swing of 1.25v p-p . both inputs are self-biased through 2.2k ? resistors, resulting in a typical differential input resistance of 4.4k ? . it is recom- mended to drive the analog inputs of the MAX1122 in ac-coupled configuration to achieve best dynamic per- formance. see the ac-coupled analog inputs section for a detailed discussion of this configuration. on-chip reference circuit the MAX1122 features an internal 1.23v bandgap ref- erence circuit (figure 3), which, in combination with an internal reference-scaling amplifier, determines the full- scale range of the MAX1122. bypass refio with a 0.1f capacitor to agnd. to compensate for gain errors or increase the adc s full-scale range, the volt- age of this bandgap reference can be indirectly adjust- ed by adding an external resistor (e.g., 100k ? trim potentiometer) between refadj and agnd or refadj and refio. see the applications information section for a detailed description of this process. clock inputs (clkp, clkn) designed for a differential lvds clock input drive, it is recommended to drive the clock inputs of the MAX1122 with an lvds-compatible clock to achieve the best MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications ______________________________________________________________________________________ 11 inp inn d0p/n d9p/n orp/n clkp clkn t ch t cl dclkp dclkn n - 8 n - 7 n n + 1 t pdl n - 7 n - 8 n n + 1 n n + 1 n + 8 n + 9 t cpdl t latency t ad n - 1 sampling event sampling event sampling event sampling event t cpdl - t pdl t cpdl - t pdl ~ 0.4 x t sample with t sample = 1/f sample note: the adc samples on the rising edge of clkp. the rising edge of dclkp can be used to externally latch the output data. figure 4. system and output timing diagram ov cc ognd 2.2k ? 2.2k ? v op v on figure 5. simplified lvds output architecture
MAX1122 dynamic performance. the clock signal source must be a high-quality, low phase noise to avoid any degrada- tion in the noise performance of the adc. the clock inputs (clkp, clkn) are internally biased to 1.2v, accept a differential signal swing of 0.2v p-p to 1.0v p-p and are usually driven in ac-coupled configuration. see the differential, ac-coupled clock input in the applications information section for more circuit details on how to drive clkp and clkn appropriately. although not recommended, the clock inputs also accept a single-ended input signal. the MAX1122 also features an internal clock manage- ment circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs clkp and clkn is processed to provide a 50% duty cycle clock signal, which desensitizes the performance of the converter to variations in the duty cycle of the input clock source. note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock fre- quency of >20mhz to work appropriately and accord- ing to data sheet specifications. clock outputs (dclkp, dclkn) the MAX1122 features a differential clock output, which can be used to latch the digital output data with an external latch or receiver. additionally, the clock output can be used to synchronize external devices (e.g., fpgas) to the adc. dclkp and dclkn are differential outputs with lvds-compatible voltage levels. there is a 2.1ns delay time between the rising (falling) edge of clkp (clkn) and the rising edge of dclkp (dclkn). see figure 4 for timing details. divide-by-2 clock control (clkdiv) the MAX1122 offers a clock control line (clkdiv), which supports the reduction of clock jitter in a system. connect clkdiv to ov cc or an lvcmos-compatible voltage level to enable the adc s internal divide-by-2 clock divider. data is now updated at one-half the adc s input clock rate. connecting clkdiv to ognd allows data to be updated at the speed of the adc input clock. clkdiv has an internal pulldown resistor and can be left open for applications that only operate with update rates identical to the converter s sampling rate. system timing requirements figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. the MAX1122 samples on the rising (falling) edge of clkp (clkn). output data is valid on the next rising (falling) edge of the dclkp (dclkn) clock, but has an internal latency of nine clock cycles. 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 12 ______________________________________________________________________________________ inp analog voltage level inn analog voltage level out-of-range orp (orn) binary digital output code (d9 d0) two s complement digital output code (d9 d0) > v cm + 0.625v < v cm - 0.625v 1 (0) 11 1111 1111 (exceeds positive full scale, or set) 01 1111 1111 (exceeds positive full scale, or set) v cm + 0.625v v cm - 0.625v 0 (1) 11 1111 1111 (represents positive full scale) 01 1111 1111 (represents positive full scale) v cm v cm 0 (1) 10 0000 0000 or 01 1111 1111 (represents midscale) 00 0000 0000 or 11 1111 1111 (represents midscale) v cm - 0.625v v cm + 0.625v 0 (1) 00 0000 0000 (represents negative full scale) 10 0000 0000 (represents negative full scale) < v cm - 0.625v > v cm + 0.625v 1 (0) 00 0000 0000 (exceeds negative full scale, or set) 10 0000 0000 (exceeds negative full scale, or set) table 1. MAX1122 digital output coding
digital outputs (d0p/n?9p/n, dclkp/n, orp/n) and control input t /b the digital outputs d0p/n d9p/n, dclkp/n, and orp/n are lvds compatible, and data on d0p/n d9p/n is presented in either binary or two s complement format (table 1). the t /b control line is an lvcmos-compatible input, which allows the user to select the desired output format. pulling t /b low out- puts data in two s complement and pulling it high pre- sents data in offset binary format on the 10-bit parallel bus. t /b has an internal pulldown resistor and may be left unconnected in applications using only two s com- plement output format. all lvds outputs provide a typi- cal voltage swing of 0.4v around a common-mode voltage of approximately 1.2v, and must be terminated at the far end of each transmission line pair (true and complementary) with 100 ? . the lvds outputs are pow- ered from a separate power supply, which can be operated between 1.7v and 1.9v. the MAX1122 offers an additional differential output pair (orp, orn) to flag out-of-range conditions, where out of range is above positive or below negative full scale. an out-of-range condition is identified with orp (orn) transitioning high (low). note: although differential lvds reduces single-ended transients to the supply and ground planes, capacitive loading on the digital outputs should still be kept as low as possible. using lvds buffers on the digital outputs of the adc when driving off-board may improve overall performance and reduce system timing constraints. applications information full-scale range adjustments using the internal bandgap reference the MAX1122 supports a full-scale adjustment range of 10% ( 5%). to decrease the full-scale range, an exter- nal resistor value ranging from 13k ? to 1m ? may be added between refadj and agnd. a similar approach can be taken to increase the adcs full-scale range. adding a variable resistor, potentiometer, or MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications ______________________________________________________________________________________ 13 reference buffer refio refadj av cc av cc / 2 control line to disable reference buffer adc full-scale = reft - refb g 1v 0.1 f reference- scaling amplifier reft refb 13k ? to 1m ? 13k ? to 1m ? figure 6. circuit suggestions to adjust the adc? full-scale range MAX1122 50 ? clkp clkn single-ended input terminal mc100lvel16 510 ? 510 ? 150 ? 150 ? v clk vgnd 2 3 45 6 7 8 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 10 d0p/n d9p/n av cc ov cc agnd ognd inp inn figure 7. differential, ac-coupled, pecl-compatible clock input configuration
MAX1122 predetermined resistor value between refadj and refio increases the full-scale range of the data con- verter. figure 6 shows the two possible configurations and their impact on the overall full-scale range adjust- ment of the MAX1122. do not use resistor values of less than 13k ? to avoid instability of the internal gain regula- tion loop for the bandgap reference. differential, ac-coupled, pecl-compatible clock input the preferred method of clocking the MAX1122 is differ- entially with lvds- or pecl-compatible input levels. to accomplish this, a 50 ? reverse-terminated clock signal source with low phase noise is ac-coupled into a fast differential receiver such as the mc100lvel16 (figure 7). the receiver produces the necessary pecl output levels to drive the clock inputs of the data converter. differential, ac-coupled analog input an rf transformer provides an excellent solution to convert a single-ended source signal to a fully differen- tial signal, required by the MAX1122 for optimum dynamic performance. in general, the MAX1122 pro- vides the best sfdr and thd with fully differential input signals and it is not recommended to drive the adc inputs in single-ended configuration. in differential input mode, even-order harmonics are usually lower since inp and inn are balanced, and each of the adc inputs only requires half the signal swing compared to a single-ended configuration. figure 8 depicts a secondary-side termination of the 1:1 transformer into two separate 25 ? loads. terminating the transformer in this fashion reduces the potential effects of transformer parasitics. the source impedance combined with the shunt capacitance provided by a pc board and the adc s parasitic capacitance reduce the combined bandwidth to approximately 550mhz. single-ended, ac-coupled analog input although not recommended, the MAX1122 can be used in single-ended mode (figure 9). analog signals can be ac-coupled to the positive input inp through a 0.1f capacitor and terminated with a 50 ? resistor to agnd. the negative input should be 25 ? reverse- terminated and ac grounded with a 0.1f capacitor. grounding, bypassing, and board layout considerations the MAX1122 requires board layout design techniques suitable for high-speed data converters. this adc pro- vides separate analog and digital power supplies. the analog and digital supply voltage pins accept input voltage ranges of 1.7v to 1.9v. although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switch- ing currents, which can couple into the analog supply network. isolate analog and digital supplies (av cc and ov cc ) where they enter the pc board with separate 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 14 ______________________________________________________________________________________ MAX1122 10 d0p/n d9p/n av cc ov cc agnd ognd inp inn 25 ? 25 ? 15 ? 15 ? adt1 1wt 0.1 f 0.1 f single-ended input terminal figure 8. transformer-coupled analog input configuration with secondary-side termination MAX1122 10 d0p/n d9p/n av cc ov cc agnd ognd 0.1 f single-ended input terminal 0.1 f inp inn 50 ? 25 ? figure 9. single-ended ac-coupled analog input configuration
networks of ferrite beads and capacitors to their corre- sponding grounds (agnd, ognd). to achieve optimum performance, provide each supply with a separate network of a 47f tantalum capacitor in parallel with 10f and 1f ceramic capacitors. additionally, the adc requires each supply pin to be bypassed with separate 0.1f ceramic capacitors (figure 10). locate these capacitors directly at the adc supply pins or as close as possible to the MAX1122. choose surface-mount capacitors, which are preferably located on the same side as the converter, to save space and minimize the inductance. multilayer boards with separated ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the adc s package. the two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. a major concern with this approach are the dynamic currents that may need to travel long dis- tances before they are recombined at a common source ground, resulting in large and undesirable ground loops. ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. to minimize the effects of digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching currents away from the sensitive analog sec- tions of the adc. this does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. the MAX1122 is packaged in a 68-pin qfn-ep pack- age (package code: g6800-4), providing greater design flexibility, increased thermal efficiency, and opti- mized ac performance of the adc. the ep must be soldered down to agnd. in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the package to the pc board with standard infrared (ir) flow soldering techniques. note that thermal efficiency is not the key factor, since the MAX1122 features low-power operation. the exposed pad is the key element to ensure a solid ground connection between the dac and the pc board s analog ground layer. considerable care must be taken, when routing the digital output traces for a high-speed, high-resolution data converter. it is essential to keep trace lengths at a minimum and place minimal capacitive loading less than 5pf on any digital trace to prevent coupling to sensitive analog sections of the adc. it is recommend- ed to run the lvds output traces as differential lines with 100 ? characteristic impedance from the adc to the lvds load device. MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications ______________________________________________________________________________________ 15 MAX1122 10 d0p/n d9p/n av cc ov cc agnd ognd ognd agnd analog power- supply source digital/output- driver power- supply source bypassing adc level bypassing board level note: each power-supply pin (analog and digital) should be decoupled with an individual 0.1 f capacitor close to the adc. 1 f10 f47 f av cc 0.1 f 0.1 f 1 f10 f47 f ov cc figure 10. grounding, bypassing, and decoupling recommendations for the MAX1122
MAX1122 static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. however, the static linearity parameters for the MAX1122 are mea- sured using the histogram method with an input fre- quency of 10mhz. differential nonlinearly (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. the MAX1122 s dnl specification is measured with the his- togram method based on a 10mhz input tone. dynamic parameter definitions aperture jitter figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 11). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, other noise sources such as thermal noise, clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the snr calcula- tion and should be considered when determining the snr in adc. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components excluding the fundamen- tal and the dc offset. in case of the MAX1122, sinad is computed from a curve fit. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the adc s full-scale range. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -7db full scale. 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications 16 ______________________________________________________________________________________ hold analog input sampled data (t/h) t/h t ad t aj track track clkn clkp figure 11. aperture jitter/delay specifications part resolution (bits) speed grade (msps) max1123 10 210 max1124 10 250 max1121 8 250 pin-compatible higher speed/ lower resolution versions
MAX1122 1.8v, 10-bit, 170msps analog-to-digital converter with lvds outputs for wideband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm

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